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Features
* Low-voltage and Standard-voltage Operation
- 2.7 (VCC = 2.7V to 5.5V) - 2.5 (VCC = 2.5V to 5.5V) - 1.8 (VCC = 1.8V to 5.5V) User-selectable Internal Organization - 1K: 128 x 8 or 64 x 16 - 2K: 256 x 8 or 128 x 16 - 4K: 512 x 8 or 256 x 16 3-wire Serial Interface 2 MHz Clock Rate (5V) Self-timed Write Cycle (10 ms max) High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Automotive Grade and Extended Temperature Devices Available 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC and 8-lead TSSOP Packages
*
* * * * * *
3-wire Serial EEPROMs
1K (128 x 8 or 64 x 16) 2K (256 x 8 or 128 x 16) 4K (512 x 8 or 256 x 16)
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 64/128/256 words of 16 bits each, when the ORG pin is connected to VCC and 128/256/512 words of 8 bits each when it is tied to ground. The device is optimized for use in many industrial and commercial applications where low power and low voltage operations are essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC and 8-lead TSSOP packages. (continued)
AT93C46 AT93C56 AT93C66
Pin Configurations
Pin Name CS SK DI DO GND VCC ORG DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Internal Organization Don't Connect 8-lead SOIC 8-lead PDIP
CS SK DI DO
1 2 3 4
8 7 6 5
VCC DC ORG GND
8-lead SOIC Rotated (R) (1K JEDEC Only)
CS SK DI DO
1 2 3 4
8 7 6 5
VCC DC ORG GND
8-lead TSSOP
DC VCC CS SK
1 2 3 4
8 7 6 5
ORG GND DO DI
CS SK DI DO
1 2 3 4
8 7 6 5
VCC DC ORG GND
Rev. 0172Q-SEEPR-08/02
1
The AT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought "high" following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Block Diagram
Note:
1. When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected. The feature is not available on the 1.8V devices. 2. For the AT93C46, if x 16 organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends using the AT93C46A device. For more details, see the AT93C46A datasheet.
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AT93C46/56/66
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol COUT CIN Note: Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI) 1. This parameter is characterized and is not 100% tested. Max 5 5 Units pF pF Conditions VOUT = 0V VIN = 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol VCC1 VCC2 VCC3 VCC4 ICC ISB1 ISB2 ISB3 ISB4 IIL IOL VIL1(1) VIH1(1) VIL2(1) VIH2(1) VOL1 VOH1 VOL2 VOH2 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage READ at 1.0 MHz Supply Current Standby Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC = 5.0V VCC = 1.8V VCC = 2.5V VCC = 2.7V VCC = 5.0V VIN = 0V to VCC VIN = 0V to VCC 4.5V VCC 5.5V 1.8V VCC 2.7V 4.5V VCC 5.5V 1.8V VCC 2.7V IOL = 2.1 mA IOH = -0.4 mA IOL = 0.15 mA IOH = -100 A VCC - 0.2 2.4 0.2 -0.6 2.0 -0.6 VCC x 0.7 WRITE at 1.0 MHz CS = 0V CS = 0V CS = 0V CS = 0V Test Condition Min 1.8 2.5 2.7 4.5 0.5 0.5 0 6.0 6.0 17 0.1 0.1 Typ Max 5.5 5.5 5.5 5.5 2.0 2.0 0.1 10.0 10.0 30 1.0 1.0 0.8 VCC + 1 VCC x 0.3 VCC + 1 0.4 Unit V V V V mA mA A A A A A A V V V V V V
1. VIL min and VIH max are reference only and are not tested.
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AC Characteristics
Applicable over recommended operating range from TA = -40C to + 85C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter SK Clock Frequency Test Condition 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Min 0 0 0 0 250 250 500 1000 250 250 500 1000 250 250 500 1000 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V Typ Max 2 1 0.5 0.25 Units
fSK

5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V
MHz
tSKH
SK High Time
ns
tSKL
SK Low Time
ns
tCS
Minimum CS Low Time
ns
tCSS
CS Setup Time
Relative to SK
VCC VCC VCC VCC VCC VCC VCC VCC
5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V
50 50 100 200 100 100 200 400 0
ns
tDIS
DI Setup Time
Relative to SK
ns
tCSH
CS Hold Time
Relative to SK 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V 4.5V 2.7V 2.5V 1.8V
ns
tDIH
DI Hold Time
Relative to SK
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V
100 100 200 400 250 250 500 1000 250 250 500 1000 250 250 500 1000 100 100 200 400 10
ns
tPD1
Output Delay to `1'
AC Test
ns
tPD0
Output Delay to `0'
AC Test
ns
tSV
CS to Status Valid
AC Test
ns
tDF
CS to DO in High Impedance
AC Test CS = VIL
ns
ms ms Write Cycles
tWP Endurance
(1)
Write Cycle Time 5.0V, 25C, Page Mode
4.5V VCC 5.5V 1M
3
Note:
1. This parameter is characterized and is not 100% tested.
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AT93C46/56/66
Instruction Set for the AT93C46
Instruction READ EWEN ERASE WRITE ERAL WRAL EWDS SB 1 1 1 1 1 1 1 Op Code 10 00 11 01 00 00 00 Address x8 A6 - A0 11XXXXX A6 - A0 A6 - A0 10XXXXX 01XXXXX 00XXXXX x 16 A5 - A0 11XXXX A5 - A0 A5 - A0 10XXXX 01XXXX 00XXXX D7 - D 0 D15 - D0 D7 - D 0 D15 - D0 x8 Data x 16 Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Erase memory location A n - A0. Writes memory location An - A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. Writes all memory locations. Valid only at VCC = 4.5V to 5.5V. Disables all programming instructions.
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Functional Description
The AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic "1") followed by the appropriate Op Code and the desired memory Address location. READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic "0") precedes the 8- or 16-bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the Erase/Write Enable state, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical "1" state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic "1" at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic "0" at DO indicates that programming is still in progress. A logic "1" indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A READY/BUSY status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle, tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic "1" state and is primarily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.
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AT93C46/56/66
Timing Diagrams
Synchronous Data Timing
Note:
1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C46 (1K) I/O AN DN Notes: x8 A6 D7 x 16 A5 D15 x8 A8
(1)
AT93C56 (2K) x 16 A7
(2)
AT93C66 (4K) x8 A8 D7 x 16 A7 D15
D7
D15
1. A8 is a DON'T CARE value, but the extra clock is required. 2. A7 is a DON'T CARE value, but the extra clock is required.
READ Timing
tCS
High Impedance
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0172Q-SEEPR-08/02
EWEN Timing
CS tCS
SK
DI
1
0
0
1
1
...
EWDS Timing
CS tCS
SK
DI
1
0
0
0
0
...
WRITE Timing
CS tCS
SK
DI
1
0
1
AN
...
A0
DN
...
D0
DO
HIGH IMPEDANCE
BUSY
READY
tWP
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AT93C46/56/66
WRAL Timing(1)
CS tCS
SK
DI
1
0
0
0
1
...
DN
...
D0
DO
HIGH IMPEDANCE
BUSY READY
tWP
Note: 1. Valid only at VCC = 4.5V to 5.5V.
ERASE Timing
tCS CS
CHECK STATUS STANDBY
SK
DI
1
1
1
AN AN-1 AN-2
...
A0 tSV tDF
HIGH IMPEDANCE READY
DO
HIGH IMPEDANCE
BUSY
tWP
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ERAL Timing(1)
tCS CS
CHECK STATUS STANDBY
SK
DI
1
0
0
1
0 tSV tDF
HIGH IMPEDANCE READY
DO
HIGH IMPEDANCE
BUSY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
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AT93C46/56/66
AT93C46 Ordering Information
Ordering Code AT93C46-10PI-2.7 AT93C46-10SI-2.7 AT93C46R-10SI-2.7 AT93C46W-10SI-2.7 AT93C46-10TI-2.7 AT93C46-10PI-1.8 AT93C46-10SI-1.8 AT93C46R-10SI-1.8 AT93C46W-10SI-1.8 AT93C46-10TI-1.8 Note: Package 8P3 8S1 8S1 8S2 8A2 8P3 8S1 8S1 8S2 8A2 Operation Range Industrial (-40C to 85C)
Industrial (-40C to 85C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type 8P3 8S1 8S2 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 R Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V) Rotated Pinout
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0172Q-SEEPR-08/02
AT93C56 Ordering Information
Ordering Code AT93C56-10PI-2.7 AT93C56-10SI-2.7 AT93C56W-10SI-2.7 AT93C56-10TI-2.7 AT93C56-10PI-1.8 AT93C56-10SI-1.8 AT93C56W-10SI-1.8 AT93C56-10TI-1.8 Note: Package 8P3 8S1 8S2 8A2 8P3 8S1 8S2 8A2 Operation Range Industrial (-40C to 85C)
Industrial (-40C to 85C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type 8P3 8S1 8S2 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V)
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AT93C46/56/66
0172Q-SEEPR-08/02
AT93C46/56/66
AT93C66 Ordering Information
Ordering Code AT93C66-10PI-2.7 AT93C66-10SI-2.7 AT93C66W-10SI-2.7 AT93C66-10TI-2.7 AT93C66-10PI-1.8 AT93C66-10SI-1.8 AT93C66W-10SI-1.8 AT93C66-10TI-1.8 Note: Package 8P3 8S1 8S2 8A2 8P3 8S1 8S2 8A2 Operation Range Industrial (-40C to 85C)
Industrial (-40C to 85C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type 8P3 8S1 8S2 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V)
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0172Q-SEEPR-08/02
Packaging Information
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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AT93C46/56/66
0172Q-SEEPR-08/02
AT93C46/56/66
8S1 - JEDEC SOIC
3
2
1
H
N
Top View
e B A
D
Side View
SYMBOL A
COMMON DIMENSIONS (Unit of Measure = mm) MIN - - - - - NOM - - - - - 1.27 BSC - - - - 6.20 1.27 MAX 1.75 0.51 0.25 5.00 4.00 NOTE
A2
C
B C D E
L E
e H L
End View
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. A
R
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0172Q-SEEPR-08/02
8S2 - EIAJ SOIC
1
H
N
Top View
e
b
A
D
Side View
SYMBOL
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A
1.78 0.05 0.35 0.18 5.13 5.13 7.62 0.51 1.27 BSC
2.03 0.33 0.51 0.25 5.38 5.41 8.38 0.89 4 2, 3 5 5
A1 L E
C
A1 b C D E
End View
H L e
Notes: 1. 2. 3. 4. 5.
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.
5/2/02 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. REV. B
R
2325 Orchard Parkway San Jose, CA 95131
8S2
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AT93C46/56/66
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AT93C46/56/66
8A2 - TSSOP
3 21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
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0172Q-SEEPR-08/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
0172Q-SEEPR-08/02 xM

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